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Espressif Systems /ESP32-C2 /SPI2 /USER1

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Interpret as USER1

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31282724232019161512118743000000000000000000000000000000000000000000USR_DUMMY_CYCLELEN0 (MST_WFULL_ERR_END_EN)MST_WFULL_ERR_END_EN0CS_SETUP_TIME0CS_HOLD_TIME0USR_ADDR_BITLEN

Description

SPI USER control register 1

Fields

USR_DUMMY_CYCLELEN

The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
MST_WFULL_ERR_END_EN

1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
CS_SETUP_TIME

(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
CS_HOLD_TIME

delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
USR_ADDR_BITLEN

The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data